VLSI design and verification

Summary

I am a graduate did my engineering in ECE stream . Specially trained in the field of VLSI for design and verification role. I have good knowledge in hardware descriptive languages like Verilog,system Verilog and UVM. Looking forward for job opportunities in this field

Expectations

Expecting good guidance which will help me as well as the company to grow

Employment Preferences

Expected Base Salary

**0,000 INR

Academic Degree

Experience

Skills

• Verilog
• System Verilog
• UVM
• Java