Verification engineer

Summary

I am a highly skilled semiconductor engineer with extensive experience in digital design, verification, and validation, specializing in Verilog, SystemVerilog, and UVM (Universal Verification Methodology). Over the years, I have successfully developed, implemented, and verified complex digital systems, collaborating with cross-functional teams to deliver high-quality semiconductor products.

Proficient in both Verilog and SystemVerilog, I have a deep understanding of RTL (Register Transfer Level) design, simulation, and synthesis, enabling the creation of efficient, high-performance designs. My expertise extends to writing testbenches, assertions, and constraints for thorough functional verification. I have extensive experience using UVM for structured, reusable, and scalable verification environments, ensuring comprehensive functional coverage and debugging in complex system-on-chip (SoC) designs.

I have hands-on experience with industry-standard EDA tools such as ModelSim, VCS, Questa, and Synopsys tools for simulation, static timing analysis, and design optimization. My skills include debugging issues in both RTL and verification environments, ensuring the timely identification and resolution of design flaws.

With a proven track record in the full verification lifecyclefrom test plan development to final sign-offI am committed to driving the success of semiconductor projects by delivering robust, high-quality solutions.

Expectations

Verification engineer, design verification engineer

Employment Preferences

Expected Base Salary

**0,000 INR

Academic Degree

Experience

Skills

• Verilog
• System Verilog
• UVM
• Coverage
• Assertions
• Regressions
• Testcases
• AHB APB PROTOCOLs
• AXI
• DDR