Semiconductor Process Engineer

Summary

2-Mask NMOS Processing Development (Cleanroom)
Measured wafer resistivity and estimated dopant concentration using 4-Probe Measurement and dopant type of test wafer using Hot Probe techniques to be verified with vendor specifications.
Aligned and exposed wafers using Cobilet Model CA-800 Aligner so as to print the desired NMOS pattern onto the wafer and generated active regions by etching exposed wafer areas and stripping photoresist.
Diffused wafers by applying spin on dopant (N type) for DOSE process followed by drive in diffusion and deposited Aluminum metal layer using thermal evaporator and etched for desired metal contacts.

Expectations

I am looking for plenty of learning and growth opportunities, a challenging and multi-cultural work environment. I expect to work in a place where my ideas and effort are appreciated and valued.

Employment Preferences
Expected Base Salary

**,000 USD

Academic Degree
Experience

Total Professional Experience

no experience
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