RTL and Physical Design Role

Summary

I am a graduate of IIT Jammu with a CGPA of 9.04. I have completed several projects in the VLSI domain, covering both analog and digital design. I am proficient in Verilog and VHDL, and have hands-on experience with industry-standard tools such as Xilinx, Cadence Virtuoso, Genus, and Innovus. With this background, I am well-suited for roles in RTL Design, Design Verification, Physical Design, as well as Analog Layout.

Expectations

In my new job, I expect to work on real-world VLSI design tasks where I can apply the concepts and tools I have learned through my academic projects and hands-on experience. Whether my role is in RTL design, verification, physical design, or analog layout, I look forward to contributing to the design and development process using tools like Cadence Virtuoso, Genus, Innovus, and Xilinx. I expect to collaborate with experienced professionals, follow established design flows, and receive guidance that will help me grow both technically and professionally. I see this opportunity as a platform to deepen my skills and gain practical exposure to the complete chip design cycle.

Employment Preferences

Expected Base Salary

*,*00,000 INR

Expected Hourly Rate

*,*00 INR/hr

Academic Degree

Experience

Skills

• Verilog
• VHDL
• Xilinx
• Synopsys DCShell
• Cadence Virtuoso
• Genus
• Innovus