RTL Logic Designer

Summary

RTL Designer and Subsystem Owner Aruba Networks ASICs

Responsible for the design and ownership of a key subsystem managing port functionality in Aruba Networks ASICs.
- Led micro-architecture definition and authored hardware specification documents.
- Collaborated closely with verification, SDK, and post-silicon teams during bring-up and validation phases.
- Served as technical lead for a team of 45 engineers, overseeing design quality and task execution.
- Acted as a mentor and trainer for new engineers, supporting onboarding and knowledge transfer.

Expectations

I am looking for a position that offers the opportunity to work on technically challenging and meaningful projects, where I can apply my skills while continuing to grow professionally through collaboration, learning, and innovation. I value environments that encourage ownership, continuous improvement, and cross-functional teamwork, and Im eager to contribute to a team where I can have both impact and long-term development.

Employment Preferences

Expected Base Salary

**0,000 USD

Academic Degree

Experience

Skills

• Verilog
• Hardware
• Logic
• Design
• Asic
• Arch