RTL design engineer, RTL verification engineer

Summary

I have done my internship in Samsung Semiconductor India Research
I joined as Associate Engineer in SoC design RTL team
I have performed sanity checks and designed on chip protocols like AXI , APB and verification of those using System verilog

Expectations

Good learning environment

Employment Preferences

Expected Base Salary

*,*00,000 INR

Academic Degree

Experience

Skills

• System Verilog
• Verilog
• Digital Design
• Perl
• Python
• On Chip Communication Protocols