RTL Design Engineer

Summary

I'm an RTL Design Engineer with 2.2 years of experience.

I have the skill set of VHDL, Verilog, Xilinx Vivado, JTAG testing.

I have completed my MTech in VLSI and Embedded Systems and BTech in Electronics and Communication Engineering.

Expectations

Looking towards job in RTL Design Engineering or RTL Verification Engineering.

Employment Preferences

Expected Base Salary

**0,000 INR

Academic Degree

Experience

Skills

• VHDL
• Verilog
• Xilinx Vivado
• JTAG Testing