IC layout design engineer

Summary

Worked and experienced with many different node technologies from old to fine nodes such as 90,65,45,28,16,10,7 and 5nm.
And have experienced for many different blocks such as SERDES , PLL , filters and charge pomps , ADC and VCO and big blocks for ESD in GPIO format
experienced for mask design in memory peripheral such as X and Y decoder and registers in different 4,8,16,32 and 64 bits.
Setup and leads for different STD cells in different TSMC nodes in high speed or normal or high performance and many more projects.

Expectations

The technology world is growing fast and working in edge of technology is the most exited things for me when I see and I feel I was a part of this amazing process.
I always like to ride with unsaddled horse.
I love to work with the design teams which have same feeling.

Employment Preferences

Expected Base Salary

**0,000 USD

Expected Hourly Rate

** USD/hr

Academic Degree

Experience

Skills

• CMOS
• FINFet
• ANALOG
• STD Cells
• SERDES
• PLL
• IO
• CADENCE
• VIRTUOSO
• DRC. LVS. ERC.
• VERIFICATION
• ANTENNA EFFECTS
• LATCH UP
• TSMC