Design Verification engineer

Summary

Design verification role. Designed uvm and system verilig verification environment to verify the AMBA protocols. Proficient in verilog and VHDL. Good debugging skills. Programmed assertions and code coverages. Used cadence virtuoso for layout as part of academics. Good knowledge in digital electronics and have hands on experience in Xilinx Vivado , Quartus prime, Questa sim

Expectations

To improve my skill set and to be driven all the time to achieve more.

Employment Preferences

Expected Base Salary

**,000 USD

Expected Hourly Rate

** USD/hr

Academic Degree

Experience

Skills

• VHDL
• Verilog
• System Verilog
• UVM
• C