Design verification Engineer

Summary

I well trained 1 year on design verification. Iam good at digital electronics, verilog, system verilog, UVM testbench verification and python programming. I have a goal to join a VLSI industry to grow my carrier as well as organization goals.

Expectations

As company requirements iam freely to work.

Employment Preferences

Expected Base Salary

**0,000 INR

Academic Degree

Experience

Skills

• Digital Electronics
• Verilog
• System Verilog
• UVM
• Python