ASIC Formal Verification Engineer

Embedded & Robotics Programming Lahore, Punjab, Pakistan

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Summary

About 4 years of experience in RTL Design and Formal Verification of RISC-V scalar and vector
architectures, floating-point arithmetic units, and DSP-oriented datapaths. Strong exposure to ASIC development
flows, simulation-based verification, and formal property checking.

Specialization: Focused expertise in RISC-V ISA interpretation, vector extension (RVV), arithmetic datapath
design and IEEE-754 floating-point units.

Verification Strengths: Proficient in Formal Verification using Synopsys VC Formal (HECTOR, C2RTL/Datapath
Verification) and dynamic verification using SystemVerilog and Python-based CocoTB. Skilled at developing
assertions, analyzing proofs, debugging convergence failures, and identifying complex corner-case arithmetic bugs.

Technical Capabilities: Experienced in building C reference models for vector arithmetic and DSP algorithms,
optimizing RTL based on timing analysis, performing microarchitecture-level design reviews, and validating hardware
functionality through emulation on AWS EC2 Cloud FPGAs.

Key Achievements: Formally verified IEEE-754 compliant floating-point unit and identified 50+ critical arithmetic
bugs. Contributed to open-source RISC-V tooling and FPGA deployment flows under CHIPS Alliance.

Career Focus: Pursuing roles in Formal Verification, with interests in
high-performance arithmetic units and vector architectures

Expectations

Pursuing roles in Formal Verification of digital designs of RISCV based CPU architecture, with interests in
high-performance arithmetic and vector units.
A learning environment and friendly workplace culture in case of onsite job.