Analog Layout Engineer

Electrical Engineering Professional Jalandhar, Punjab, India

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Summary

1) Voltage-controlled oscillators consume much power (between 2-5 uW). Current Starved VCO is one type of low power VCO but still its power ranges from 1.5uW to 4uW. (These numbers are based on my results conducted on Cadence Virtuoso).
2) The future scope of ring oscillators is promising and expanding, especially as electronics continue to evolve in the areas of high-speed communication, low-power design, and integration with emerging technologies. So, with these many applications, there must be a better circuit topology to use in each case.
3) First, I have done a literature review and selected 5 current starved ring oscillators, which I will be using to conduct the analysis. The circuits were Conventional CSVCO, NMOS Sink CSVCO, PMOS Sink CSVCO, Symmetric Load CSVCO and Output Switch Scheme CSVCO. Then, I have fixed the sizing of each circuit such that each one has a proper swing. But for proper swing, I have to add a buffer such that, at minimum sizing, these should work for minimum power consumption. So, I conducted parametric, process corner, and Monte Carlo analysis for each circuit with varying Vdd, Vctrl and Temperature. Then I choose various different inverter topologies such that the new circuit has some better results in terms of power, phase noise, settling time, and frequency. Some of the topologies I used were Lector, Schmitt Trigger, Galeor, Transmission Gate, and Unsymmetrical Load CSVCO. Unfortunately, I didn't get promising results for all the different topologies I used.
4) From the analysis, I found which circuit to use in which situation.
For minimum phase noise (-74.6 dBc/Hz), Conventional CSVCO.
For maximum frequency, (904.1 MHz), PMOS Sink CSVCO
For minimum settling time (65.1 ps), NMOS Sink CSVCO.
For minimum power (1.88 uW), Output Switch Scheme CSVCO.
For all the factors in a good range, Symmetric Load CSVCO.

Expectations

I can expect to take on responsibilities involving low-power analog and mixed-signal circuit design, with a focus on optimizing performance metrics such as power consumption, frequency stability, phase noise, and settling time. My proficiency in Cadence Virtuoso and experience with advanced simulation methodsincluding parametric, corner, and Monte Carlo analysisprepare me well for roles involving the design and validation of components like voltage-controlled oscillators, phase-locked loops, and clock generators. I have developed a strong understanding of circuit-level trade-offs and system-level requirements, which will help me contribute effectively to areas such as RFIC development, ultra-low-power systems, and secure hardware design.